onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -divider Top-Level
add wave -noupdate -radix hexadecimal /tb_cpu/writeTrack
add wave -noupdate -radix hexadecimal /tb_cpu/viewMemWen
add wave -noupdate -radix hexadecimal /tb_cpu/viewMemAddr
add wave -noupdate -radix hexadecimal /tb_cpu/nReset
add wave -noupdate -radix hexadecimal /tb_cpu/myMemWen
add wave -noupdate -radix hexadecimal /tb_cpu/myMemData
add wave -noupdate -radix hexadecimal /tb_cpu/myMemCtl
add wave -noupdate -radix hexadecimal /tb_cpu/myMemAddr
add wave -noupdate -radix hexadecimal /tb_cpu/memQ
add wave -noupdate -radix hexadecimal /tb_cpu/memNReset
add wave -noupdate -radix hexadecimal /tb_cpu/initClkCtl
add wave -noupdate -radix hexadecimal /tb_cpu/imemData
add wave -noupdate -radix hexadecimal /tb_cpu/imemAddr
add wave -noupdate -radix hexadecimal /tb_cpu/hexOut
add wave -noupdate -radix hexadecimal /tb_cpu/halt
add wave -noupdate -radix hexadecimal /tb_cpu/dumpClkCtl
add wave -noupdate -radix hexadecimal /tb_cpu/dmemDataWrite
add wave -noupdate -radix hexadecimal /tb_cpu/dmemAddr
add wave -noupdate -radix hexadecimal /tb_cpu/dipIn
add wave -noupdate -radix hexadecimal /tb_cpu/cpuClkCtl
add wave -noupdate -radix hexadecimal /tb_cpu/cpuClk
add wave -noupdate -radix hexadecimal /tb_cpu/clk
add wave -noupdate -radix hexadecimal /tb_cpu/address
add wave -noupdate -divider CPU
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/clk
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/t_instruction
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/nReset
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/nPC
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/invalidate
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/instruction
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/iMemWait
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/iMemRen
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/iMemData
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/iMemAddr
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/hold
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/halt
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/destination
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/dMemWen
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/dMemWait
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/dMemRen
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/dMemDataW
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/dMemDataR
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/dMemAddr
add wave -noupdate -divider fetch
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/sel
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/pcplusfour
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/pcout
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/pcOld_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/pcOld
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/nReset
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/nPC
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/jumpAddr
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/invalidate
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/instruction
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/iMemData
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/iMemAddr
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/holdStage
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/holdPC
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/halt
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/clk
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/fetch_c/busA
add wave -noupdate -divider id
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/writeDestination
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/writeData
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/upper
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/t_upper
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/t_shftamnt
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/t_imm16
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/shftamnt
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/rt
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/rs
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/rdat2
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/rdat1
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/rd
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/pcOld_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/pcOld
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/opcode
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/op
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/nReset
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/nPC_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/nPC_Sel
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/nPC
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/jumpAddr
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/invalidate
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/instruction_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/instruction
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/immediate
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/holdStage
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/halt
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/fnct
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/extend
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/extImm
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/equal
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/destination
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/clk
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/busB
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/busA
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/id_c/Wen
add wave -noupdate -divider exec
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/upper_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/upper
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/uns
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/t_aluResult
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/shftamnt_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/op
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/nReset
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/nPC_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/nPC
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/invalidate
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/instruction_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/instruction
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/immediate_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/holdStage
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/fullShftamnt
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/destination_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/destination
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/clk
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/busB_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/busB
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/busA_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/alu_opcode
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/aluSrc_result
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/exec_c/aluResult
add wave -noupdate -divider mem
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/upper_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/upper
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/op
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/nReset
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/nPC_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/nPC
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/memWait
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/invalidate
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/instruction_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/instruction
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/holdStage
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/destination_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/destination
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/dataMem
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/dMemWen
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/dMemRen
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/dMemDataW
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/dMemDataR
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/dMemAddr
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/clk
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/busB_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/aluResult_in
add wave -noupdate -radix hexadecimal /tb_cpu/DUT/theCPU/theCPU/cpu_c/mem_c/aluResult
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {1191 ns}
